Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography, among others, is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
A lithographic process, as described above, is performed to selectively remove portions of a resist material overlaying the surface of a wafer, thereby exposing underlying areas of the specimen on which the resist is formed for selective processing such as etching, material deposition, implantation, and the like. Therefore, in many instances, the performance of the lithography process largely determines the characteristics (e.g., dimensions) of the structures formed on the specimen. Consequently, the trend in lithography is to design systems and components (e.g., resist materials) that are capable of forming patterns having ever smaller dimensions. In particular, the resolution capability of the lithography tools is one primary driver of lithography research and development.
Inspection processes based on optical metrology are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry implementations and associated analysis algorithms to characterize device geometry have been described.
A wafer is positioned within a wafer processing tool (e.g., lithography tool, etch tool, inspection tool, metrology tool, etc.) by clamping the thin wafer to a flat wafer chuck. The wafer chuck is a machine part that provides the interface between the wafer and the rest of the machine. The wafer is precisely positioned within the tool by precisely controlling the movements of the wafer chuck to which the wafer is attached. The dimensions of the surface of the wafer chuck that interfaces with the wafer are precisely manufactured and maintained during the operation of the tool.
Wafers themselves are very thin (e.g., 200 micrometers to 1.5 millimeters thick) and have relatively large diameters (e.g., 200-300 millimeters, or more). For this reason, the shape of a wafer is not particularly stable in its unconstrained (i.e., unsupported) state. This is particularly true for wafer flatness. During processing, the wafer is clamped to the wafer chuck over a large portion of its backside surface area. By forcing the wafer to conform to the shape of the wafer chuck, the wafer chuck flattens the wafer, so that wafer processing and inspection tasks can be completed successfully.
In many examples, wafers are clamped to the wafer chuck by vacuum. As the wafer is lowered onto the wafer chuck, the backside wafer surface comes into contact with the chuck and covers vacuum channels machined into the surface of the wafer chuck. As the wafer covers the vacuum channels, the vacuum supplied at the channels effectively pulls the wafer down onto the surface of wafer chuck and maintains the wafer in the clamped position as long as vacuum is maintained at the channels.
Unfortunately, this approach to clamping the wafer to the surface of the wafer chuck is problematic when the wafer is extremely warped (i.e., not flat). In some examples, 300 millimeter diameter wafers exhibit variation in flatness from hundreds of micrometers (e.g., 500 micrometers) to several millimeters (e.g., 8-10 millimeters). When a wafer is extremely warped (e.g., flatness variation exceeding one millimeter), the wafer does not uniformly cover the vacuum channels of the wafer chuck. This results in large vacuum leaks that reduce the clamping force exerted by each vacuum channel. In many scenarios, the reduced clamping force is unable to achieve adequate force levels required to pull the wafer from its deformed state down onto the wafer chuck. As a result, the wafer chuck is unable to adequately constrain the wafer and further processing of the wafer is not possible without additional intervention. In some scenarios, increased vacuum flow is able to compensate for the large leaks and generate enough force to successfully clamp the wafer. But, realizing high vacuum flows is often undesirable from both design and operational perspectives (e.g., increased design complexity and cost). In some scenarios, increased vacuum flow is not enough to overcome large leaks generated by warped wafers. In these scenarios, the wafer may have to be discarded or specially processed to reduce warpage.
Improved methods and systems for chucking warped wafers in semiconductor processing equipment are desired.